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5.1.1 Automake variable definitions

Variable definitions consist of a variable name, followed by optional whitespace, followed by an equals sign (‘=’), followed by optional whitespace, followed by the value of the variable.

Variables may also be redefined later on in the file following an existing definition with a line consisting of a variable name, followed by optional whitespace, followed by ‘+=’, followed by optional whitespace, followed by a string to append to the value of the variable. 1

Certain variables defined in the cause Automake to generate output: for instance, a bin_PROGRAMS variable definition will cause rules for compiling and linking programs to be generated.

Many variables take space-separated lists of objects as their values. For example, the value of bin_PROGRAMS is a list of programs. There are other variables, like AM_CPPFLAGS, which can contain parts of shell commands.

A variable defined in will override any definition of the variable that automake would ordinarily create. However, you should not rely on overriding any variable for which the effect of this is not documented in this manual, as the names and/or usage of such variables may change in future releases.

When examining a variable definition, Automake will substitute the values of any variables referenced in the value given. A variable may be referenced by surrounding its name either with ‘$(’ and ‘)’, or with ‘${’ and ‘}’. Any undefined variables are expanded to the empty string.

For example, if Automake is looking at the content of foo_SOURCES in this snippet

xs = a.c b.c
foo_SOURCES = c.c $(xs)

the ‘foo_SOURCES’ variable would end up with the value ‘c.c a.c b.c’, leading the files a.c, b.c, and c.c to be used as the sources for ‘foo’.



Some make programs recognize a ‘+=’ syntax, but automake will not use it in the Makefile it generates, so it doesn’t matter whether the make program in use recognizes this syntax or not.

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